module cond_decoder(
  input  [3:0] i_cond,
  input  [3:0] i_nzcv,
  output       o_pass
);

wire n,z,c,v;
assign {n,z,c,v} = i_nzcv;

reg f;

always @* begin
  case (i_cond[3:1])
    3'b000: f = z;
    3'b001: f = c;
    3'b010: f = n;
    3'b011: f = v;
    3'b100: f = c&~z;
    3'b101: f = n==v;
    3'b110: f = ~z&n==v;
    3'b111: f = 1'b1;
  endcase
end

assign o_pass = f^i_cond[0];

endmodule
